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257 IP
201
0.118
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler....
202
0.118
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy....
203
0.118
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier...
204
0.118
UMC 55nm eFlash Single-Port SRAM memory compiler
UMC 55nm eFlash Single-Port SRAM memory compiler...
205
0.118
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler....
206
0.118
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy...
207
0.118
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell...
208
0.118
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell...
209
0.118
UMC 55nm eHV process;Single-Port SRAM compiler
UMC 55nm eHV process;Single-Port SRAM compiler...
210
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
211
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
212
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
213
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
214
0.118
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler....
215
0.118
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler...
216
0.118
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler....
217
0.118
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....
218
0.118
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT...
219
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
220
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
221
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
222
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
223
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
224
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
225
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
226
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
227
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
228
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....
229
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
230
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
231
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
232
0.118
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler...
233
0.118
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy...
234
0.118
UMC 90nm SPLVT ultra-high speed 1-port SRAM
UMC 90nm SPLVT ultra-high speed 1-port SRAM...
235
0.118
Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler....
236
0.118
Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process
UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler....
237
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process
UMC 40nm Logic process synchronous high density Dual Port SRAM memory compiler with redundancy....
238
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option....
239
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Dual Port SRAM with redundancy feature....
240
0.118
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Dual Port SRAM compiler....
241
0.118
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash LL process Dual Port SRAM compiler....
242
0.118
Dual Port SRAM Compiler IP, UMC 0.11um LL process
UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler....
243
0.118
Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler....
244
0.118
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux....
245
0.118
Dual Port SRAM Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler....
246
0.118
Dual Port SRAM Compiler IP, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash GII Logic process high density Dual Port SRAM compiler....
247
0.118
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....
248
0.118
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....
249
0.118
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Dual Port SRAM compiler....
250
0.118
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT....
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